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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. o0610 sy/60910 sy 20100427-s00005 no.a1741-1/28 LV5230BG overview the LV5230BG is a dot-matrix led driver ic for cell phones. features ? 7 17 dot-matrix led driver (5 15 dot-matrix supported) ? each dot can be set for display over the serial bus. functions ? led driver column (anode) driving p-channel driver 17 channels row (cathode ) drivin g n-channel driver 7 channels led current per dot : 25ma maximum two flames of 7 17 (5 15) patterns can be set. 7 grayscale level adjustment on a do t basis (pwm duty factor switching) reverse display horizontal scroll (1 frame/2 frames) continuous/single scroll selectable vertical scroll (1 frame/2 frames) continuous/single scroll selectable automatic flashing can be specified per each dot interupt output at the end of scroll ring tone synchronization function ? led driving open drain output 2 bi-cmos ic 7ch17ch led driver orderin g numbe r : ena1741a
LV5230BG no.a1741-2/28 specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit v cc max1 sv cc , v dd 5.5 v maximum supply voltage v cc max2 ledv dd 6v allowable power dissipation pd max mounted on a board * 1.15 w operating temperature topr -30 to +85 c storage temperature tstg -40 to +125 c ? designated board : 40mm 50mm 0.8mm, glass epoxy 4-layter board (2s2p) operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage 1 v bat sv cc 3 to 4.5 v supply voltage 2 v dd v dd 1.65 to 3 v supply voltage 3 vledv dd ledv dd 2.7 to 5.5 v * power application sequence : 1. v bat 2. v dd v bat > v dd , no restriction on vledv dd . * same level of voltage ledv cc must be applied to the 4 pins as vledv dd voltage. electrical characteristics, analog block ta = 25 c, v bat = 3.7v, v dd = 2.6v, ledv dd = 3.7v, unless otherwise specified ratings parameter symbol conditions min typ max unit consumption current (sv cc +v dd +ledv dd ) consumption current 1 i cc 1 reset : l 0 5 a consumption current 2 i cc 2 reset : h, serial default 0.3 5 a consumption current 3a i cc 3a when stby mode is released, rt external resistance value is 27k 1.9 3 ma consumption current 3b i cc 3b when stby mode is released, rt external resistance value is 160k 1 2 ma ledsw on resistance 1 ron1 row1 to 7 : il = 425ma 1 2 on resistance 2 ron2 ledo1, led02 : il = 20ma 2 4 led current 1 iled1 col1 to col17 : v o = ledv dd -0.5v rt external resistance value : 27k 20 22.5 25 ma led current 2 iled2 col1 to col17 : v o = ledv dd -0.5v rt external resistance value : 160k 2.8 3.8 4.8 ma leakage current 1 il1 row1 to row : v o = 5v 1 a leakage current 2 il2 col1 to col17 : v o = 0v, ledv dd = 5v 1 a leakage current 3 il3 ledo1, led02 : v o = 5v 1 a osc oscillator frequency f1 when rt external resistance is 27k , ct external capac itance is 120pf 900 1000 1100 khz oscillator frequency f1 when rt external resistance is 160k , ct external capacitance is 10pf 900 1000 1100 khz rt maximum. led drive current setting li1 rt external resistance : 27k led maximum drive current = 607.5/rt resistance 20 22.5 25 ma continued on next page.
LV5230BG no.a1741-3/28 continued from preceding page. ratings parameter symbol conditions min typ max unit control circuit block h level 1 v inh 1 input h level, sda, scl v dd 0.8 v l level 1 v inl 1 input l level, sda, scl 0 v dd 0.2 v h level 2 v inh 2 input h level, reset, sctl 1.5 v l level 2 v inl 2 input l level, reset, sctl 0 0.3 v h input current 3 i hin 3 inflow-outflow current, when vbat voltage is applied to reset pin. -1 0 1 a l input current 3 i lin 3 inflow-outflow current, when 0v is applied to reset pin. -1 0 1 a h input current 4 i hin 4 inflow-outflow current, when vbat voltage is applied to sctl pin. 15 47 75 a l input current 4 i lin 4 inflow-outflow current, when 0v is applied to sctl pin. -1 0 1 a h output level 1 vh1 into pin, h level, i o = 1ma v dd -0.3 v dd v l output level 1 vl1 into pin, l level, i o = 1ma 0 0.3 v package dimensions unit : mm (typ) 3396 pd max - ta 0 1.2 1.0 0.6 0.8 0.4 0.2 1.4 ? 30 90 60 30 0 120 0.46 1.15 specified board : 50 40 0.8mm 3 4-layer glass epoxy (2s2p) board allowable power dissipation, pd max - w ambient temperature, ta - c sanyo : fbga49(5.0x5.0) 5.0 5.0 1234 567 0.65 0.65 abcdefg 0.55 0.55 0.10 0.95 max 0.35 side view top view bottom view
LV5230BG no.a1741-4/28 pin assignment grid pin name function protection diode vs. ledv dd protection diode vs. sv cc protection diode vs. gnd a1 test test input pin a2 rt standard current setting resistance connection pin a3 row4 row sw4 a4 ledgnd3 row sw gnd a5 ledgnd4 row sw gnd a6 row7 row sw7 a7 nc no connection b1 row2 row sw2 b2 row3 row sw3 b3 ledgnd2 row sw gnd b4 row5 row sw5 b5 row6 row sw6 b6 ledo1 led driver 1 b7 ledgnd5 ledo1,2 exclusive gnd c1 ledgnd1 row sw gnd - - - c2 row1 row sw1 c3 v dd serial i/o supply voltage c4 into int output c5 gpi receiving melody synchronous signal input pin c6 ledo2 led driver 2 c7 col1 col sw1 d1 sgnd analog logic gnd d2 sda serial data signal input d3 scl serial clock signal input d4 reset reset pin d5 col2 col sw2 d6 col3 col sw3 d7 ledv dd dot matrix led drive voltage impression pin e1 ct setting of frequency of transmitter capacitor connection pin e2 sv cc analog logic supply voltage e3 col13 col sw13 e4 col11 col sw11 e5 col4 col sw4 e6 col5 col sw5 e7 col6 col sw6 f1 col16 col sw16 f2 col17 col sw17 f3 col14 col sw14 f4 col12 col sw12 f5 col9 col sw9 f6 col8 col sw8 f7 col7 col sw7 g1 nc no connection g2 ledv dd dot matrix led drive voltage impression pin g3 col15 col sw15 g4 ledv dd dot matrix led drive voltage impression pin g5 col10 col sw10 g6 ledv dd dot matrix led drive voltage impression pin g7 nc no connection nc col16 ct sgnd ledgnd 1 row2 test ledv dd col17 sv cc sda row1 row3 rt col15 col14 col13 scl v dd ledgnd 2 row4 ledv dd col12 col11 reset into row5 ledgnd 3 col10 col9 col4 col2 gpi row6 ledgnd 4 ledv dd col8 col5 col3 ledo2 ledo1 row7 nc col7 col6 ledv dd col1 ledgnd 5 nc 1 2 3 4 5 6 7 1 2 3 4 5 6 7 gfedcba gfedcba top view
LV5230BG no.a1741-5/28 block diagram v bat pwm ledv dd row1 row2 row3 row4 ledgnd1 ledgnd2 ledgnd3 ledgnd4 row5 row6 row7 col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 col16 col17 nc nc nc sgnd sv cc ct rt reset ledgnd5 ledo1 ledo2 test gpi (sctl) into scl v dd sda osc counter shift register i 2 c bus control i/f level shift iref
LV5230BG no.a1741-6/28 dot matrix led 7 17 dynamic display dot matrix led 5 15 dynamic display row1 col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 col16 col17 row2 row3 row4 row5 row6 row7 row1 2ms row2 row3 row4 row5 row6 row7 row1 row2 row3 row4 row5 row1 col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 row2 row3 row4 row5 2ms
LV5230BG no.a1741-7/28 pin functions pin no. pin name pin description equivalent circuit a1 test test signal input pin. be sure to connect the pin to gnd. sv cc a 1 pin a2 rt reference current setting resistor connection pin. by connecting the external resistor between this pin and gnd, the reference current is generated. the pin voltage is about 0.61v. change of this current value enables change of the oscillation frequency and led driver current value (col1 to col17 only). sv cc a2 pin a3 a6 b1 b2 b4 b5 c2 row4 row7 row2 row3 row5 row6 row1 n-channel driver output pins 1 to 7 for row (cathode) drive. must be connected to gnd when not to be used. a3, a6, b1, b2, b4, b5, c2 pin a4 ledgnd3 row sw gnd. a5 ledgnd4 row sw gnd. a7 g1 g7 nc no connection. b3 ledgnd2 row sw gnd. b6 c6 ledo1 ledo2 open drain output pins for led drive. must be connected to gnd when not to be used. b6, c6 pin b7 ledgnd5 gnd pin dedicated for ledo1 and ledo2. c1 ledgnd1 row sw gnd. c3 v dd power supply for serial i/f. c4 into interrupt signal output pin. sv cc v dd c4 pin continued on next page.
LV5230BG no.a1741-8/28 continued from preceding page. pin no. pin name pin description equivalent circuit c5 gpi ringing tone synchronization signal input pin. must be connected to gnd when not to be used. sv bat c5 pin c7 d5 d6 e3 e4 e5 e6 e7 f1 f2 f3 f4 f5 f6 f7 g3 g5 col1 col2 col3 col13 col11 col4 col5 col6 col16 col17 col14 col12 col9 col8 col7 col15 col10 p-channel driver output pins 1 to 17 for column (anode) drive. must be connected to gnd when not to be used. ledv dd c7, d5, d6, e3, e4, e5, e6, e7, f1, f2, f3, f4, f5, f6, f7, g3, g5 pin d7 g2 g4 g6 ledv dd dot matrix led drive voltage supply pins. d1 sgnd analog circuit gnd pin. d2 sda serial data signal input pin. d2 pin v dd d3 scl serial clock signal input pin. d3 pin v dd continued on next page.
LV5230BG no.a1741-9/28 continued from preceding page. pin no. pin name pin description equivalent circuit d4 reset reset signal input pin. reset state when low. sv cc d4 pin e1 ct oscillator frequency setting capacitor connection pin. the oscillation frequency can be adjusted by changing the value of capacitor at ct pin. sv cc e1 pin e2 sv cc analog circuit power supply.
LV5230BG no.a1741-10/28 serial bus communication specifications i 2 c serial transfer timing conditions standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz ts1 scl setup time relative to the fall of sda 4.7 s ts2 sda setup time relative to the rise of scl 250 ns data set up time ts3 scl setup time relative to the rise of sda 4.0 s th1 scl data hold time relati ve to the fall of sda 4.0 s data hold time th2 sda hold time relative to the fall of scl 0 s twl scl pulse width for the l period 4.7 s pulse width twh scl pulse width for the h period 4.0 s ton scl and sda (input) rise time 1000 ns input waveform conditions tof scl and sda (input) fall time 300 ns bus free time tbuf time between stop and start conditions 4.7 s high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 400 khz ts1 scl setup time relative to the fall of sda 0.6 s ts2 sda setup time relative to the rise of scl 100 ns data setup time ts3 scl setup time relative to the rise of sda 0.6 s th1 scl data hold time relati ve to the fall of sda 0.6 s data hold time th2 sda hold time relative to the fall of scl 0 s twl scl pulse width for the l period 1.3 s pulse width twh scl pulse width for the h period 0.6 s ton scl and sda (input) rise time 300 ns input waveform conditions tof scl and sda (input) fall time 300 ns bus free time tbuf time between stop and start conditions 1.3 s th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbuf tof
LV5230BG no.a1741-11/28 i 2 c bus transmission method start and stop conditions in the i 2 c bus, sda must basically be kept in the constant state while scl is ?h? as shown below during data transfer. when data transfer is not made, both scl and sda are in the ?h? state. when scl = sda = ?h?, change of sda from ?h? to ?l? enables the start conditions to start access. when scl is ?h?, change of sda from ?l? to ?h? enables the stop conditions to stop access. ts2 th2 scl sda th1 ts3 scl sda start condition stop condition (ctl=h)
LV5230BG no.a1741-12/28 data transfer and acknowledgement response after establishment of start conditions, data transfer is made by one byte (8 bits). data transfer enables continuous tr ansfer of any number of bytes. each time the 8-bit data is transferred, the ack signal is sent from the receive side to the send side. the ack signal is issued when sda on the send side is re leased and sda on the receive side is set ?l? immediately after fall of the clock pulse at the scl eighth bit of data transfer to ?l?. when the next 1-byte transfer is left in the receive state after transmission of the ack signal from the receive side, the receive side releases sda at fall of the scl ninth clock. in the i 2 c bus, there is no ce signal. instead , 7-bit slave address is assigned to each device and the first byte of transfer is assigned to the command (r/w) representing the 7-bit slave address and subsequent transfer direction. the 7-bit address is transferred sequentially from msb and if the eighth bit is ?l?, the second byte is write mode and if ?h?, the second byte is read mode. in the read mode, the ack signal issued immediately before sending the stop condition must be 1. in lv5230, the slave address is specified as (1110111). start scl sda slave address register address data stop m s b l s b a c k a c k a c k w 1110111 00000010 00010001 m s b l s b m s b l s b start scl sda slave address data data status status stop m s b l s b a c k a c k a c k w 1110111 1 0 1 m s b l s b m s b l s b write mode read mode
LV5230BG no.a1741-13/28 serial modes setting address : 00h ctrl1 00h ctrl1 d7 d6 d5 d4 d3 d2 d1 d0 register name stby - mxmode mswen - dfclr fadeclr scrlclr r/w w w w w w w default 0 0 0 0 0 0 d0 : scrlclr scroll interrupt signal clear 0 : scroll interrupt signal stays active. 1 : scroll interrupt signal cleared. * automatically updated to 0 after being set to 1. d1 : fadeclr fade interrupt signal clear 0 : fade interrupt signal stays active. 1 : fade interrupt signal cleared. * automatically updated to 0 after being set to 1. d2 : dfclr pallete fade interrupt signal clear 0 : pallete fade interrupt signal stays active. 1 : pallete fade interrupt signal cleared. * automatically updated to 0 after being set to 1. d4 : mswen ringing tone synchronization enable 0 : ringing tone synchronization enabled. * gpi = l : all leds turned off, gpi = h : normal operation 1 : ringing tone synchronization disabled. d5 : mxmode led matrix mode switchingr 0 : 7 17 led matrix 1 : 5 15 led matrix d7: stby standby mode 0 : standby 1 : operation
LV5230BG no.a1741-14/28 address : 01h ctrl2 01h ctrl2 d7 d6 d5 d4 d3 d2 d1 d0 register name ledoff - led2 led1 - rothen rotven page r/w w w w w w w default 0 0 0 0 0 0 d0 : page display page 0 : frame 1 displayed 1 : frame 2 displayed d1 : rotven vertical rotation 0 : normal display 1 : vertically rotated display d2 : rothen horizontal rotation 0 : normal display 1 : horizontally rotated display d4 : led1 led1 enable 0 : led1 turned off 1 : led1 turned on d5 : led2 led2 enable 0 : led2 turned off 1 : led2 turned on d7 : ledoff screen display on/off 0 : normal operation 1 : all matrix leds turned off
LV5230BG no.a1741-15/28 address : 02h dotmode 02h dotmode d7 d6 d5 d4 d3 d2 d1 d0 register name doten dotmode - - do tsp [3] dotsp [2] do tsp [1] dotsp [0] r/w w w w w w w default 0 0 0 0 0 0 d3-d0 : dotsp flashing/brightness inversion speed d3 d2 d1 d0 0 0 0 0 on : 0.05s off : 0.05s 0 0 0 1 on : 0.10s off : 0.10s 0 0 1 0 on : 0.15s off : 0.15s 0 0 1 1 on : 0.20s off : 0.20s 0 1 0 0 on : 0.25s off : 0.25s 0 1 0 1 on : 0.30s off : 0.30s 0 1 1 0 on : 0.35s off : 0.35s 0 1 1 1 on : 0.40s off : 0.40s 1 0 0 0 on : 0.45s off : 0.45s 1 0 0 1 on : 0.50s off : 0.50s 1 0 1 0 on : 0.55s off : 0.55s 1 0 1 1 on : 0.60s off : 0.60s 1 1 0 0 on : 0.65s off : 0.65s 1 1 0 1 on : 0.70s off : 0.70s 1 1 1 0 on : 0.75s off : 0.75s 1 1 1 1 on : 0.80s off : 0.80s d6 : dotmode flashing/brightness inversion display switching 0 : flashing 1 : brightness inversion d7 : doten flashing/brightness inversion display enable 0 : disable 1 : enable
LV5230BG no.a1741-16/28 address : 03h autopage 03h autopage d7 d6 d5 d4 d3 d2 d1 d0 register name pgen - - - pg sp [3] pgsp [2] pgsp [1] pgsp [0] r/w w w w w w default 0 0 0 0 0 d3 top d0 : pgsp page switching speed d3 d2 d1 d0 0 0 0 0 page1 : 0.05s page2 : 0.05s 0 0 0 1 page1 : 0.10s page2 : 0.10s 0 0 1 0 page1 : 0.15s page2 : 0.15s 0 0 1 1 page1 : 0.20s page2 : 0.20s 0 1 0 0 page1 : 0.25s page2 : 0.25s 0 1 0 1 page1 : 0.30s page2 : 0.30s 0 1 1 0 page1 : 0.35s page2 : 0.35s 0 1 1 1 page1 : 0.40s page2 : 0.40s 1 0 0 0 page1 : 0.45s page2 : 0.45s 1 0 0 1 page1 : 0.50s page2 : 0.50s 1 0 1 0 page1 : 0.55s page2 : 0.55s 1 0 1 1 page1 : 0.60s page2 : 0.60s 1 1 0 0 page1 : 0.65s page2 : 0.65s 1 1 0 1 page1 : 0.70s page2 : 0.70s 1 1 1 0 page1 : 0.75s page2 : 0.75s 1 1 1 1 page1 : 0.80s page2 : 0.80s d7 : pgen automatic page switching enable 0 : disable 1 : enable
LV5230BG no.a1741-17/28 address : 04h sccon1 04h sccon1 d7 d6 d5 d4 d3 d2 d1 d0 register name scen scdir [1] scdir [0] scmode scsp [3] scsp [2] scsp [1] scsp [0] r/w w w w w w w w w default 0 0 0 0 0 0 0 0 d3 to d0 : scsp scroll speed per dot d3 d2 d1 d0 0 0 0 0 50ms 0 0 0 1 100ms 0 0 1 0 150ms 0 0 1 1 200ms 0 1 0 0 250ms 0 1 0 1 300ms 0 1 1 0 350ms 0 1 1 1 400ms 1 0 0 0 450ms 1 0 0 1 500ms 1 0 1 0 550ms 1 0 1 1 600ms 1 1 0 0 650ms 1 1 0 1 700ms 1 1 1 0 750ms 1 1 1 1 800ms d4 : scmode page mode when scrolling 0 : scrolls and displays the current page repeatedly. 1 : scrolls and displays the current and other pages alternately. d6 to d5 : scdir scroll direction d6 d5 0 0 right 0 1 left 1 0 up 1 1 down d7 : scen scroll enable 0 : disable 1 : enable
LV5230BG no.a1741-18/28 address : 05h sccon2 05h sccon2 d7 d6 d5 d4 d3 d2 d1 d0 register name scgo - sccnt [5] sccnt [4] sccnt [3] sccnt [2] sccnt [1] sccnt [0] r/w w w w w w w w default 0 0 0 0 0 0 0 d0 to d5 : sccnt scroll increment 17 7 mode when sccon1.scdir = 0 or 1 : 1 to 34 when sccon1.scdir = 2 or 3 : 1 to 14 15 5 mode when sccon1.scdir = 0 or 1 : 1 to 30 when sccon1.scdir = 2 or 3 : 1 to 10 * scrolls one page when sccnt = 0. d7 : scgo scroll start 0 : standby 1 : scroll start * the scrolled state is maintained until sccon1 and scen are set low.
LV5230BG no.a1741-19/28 address : 06h fadecon 06h fadecon d7 d6 d5 d4 d3 d2 d1 d0 register name fadeen fadego fadeio fademod fdsp [3] fdsp [2] fdsp [1] fdsp [0] r/w w w w w w w w w default 0 0 0 0 0 0 0 0 d3 to d0 : fdsp fade speed per 1 grayscale level (it takes (following set value 64) seconds to complete fading) d3 d2 d1 d0 0 0 0 0 2ms 0 0 0 1 4ms 0 0 1 0 6ms 0 0 1 1 8ms 0 1 0 0 10ms 0 1 0 1 12ms 0 1 1 0 14ms 0 1 1 1 16ms 1 0 0 0 18ms 1 0 0 1 20ms 1 0 1 0 22ms 1 0 1 1 24ms 1 1 0 0 26ms 1 1 0 1 28ms 1 1 1 0 30ms 1 1 1 1 32ms d4 : fademod single/continuous switching 0 : single fade-in/fade-out operation 1 : fade-in/fade-out operation repeated d5 : fadeio fade-in/fade-out switching 0 : fade in 1 : fade out d6 : fadego fade-in/fade-out start 0 : standby 1 : fade-in/fade-out operation start d7 : fadeen fade-in/fade-out enable 0 : disable 1 : enable * the interrupt flag is set high after a fade ope ration has completed. manual clearing is required. * all leds are turned off if fadeen is set to 1 when fadeo is set to 0. if go is set to 1 in that state, fade-in operation starts and leds are turned on.
LV5230BG no.a1741-20/28 address : 07h rowsw 07h rowsw d7 d6 d5 d4 d3 d2 d1 d0 register name rowswen rowsw7 rowsw6 rowsw5 rowsw4 rowsw3 rowsw2 rowsw1 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 d0 : rowsw1 row 1 display on/off 0 : on 1 : off d1 : rowsw2 row 2 display on/off 0 : on 1 : off d2 : rowsw3 row 3 display on/off 0 : on 1 : off d3 : rowsw4 row 4 display on/off 0 : on 1 : off d4 : rowsw5 row 5 display on/off 0 : on 1 : off d5 : rowsw6 row 6 display on/off 0 : on 1 : off d6 : rowsw7 row 7 display on/off 0 : on 1 : off d7 : rowswen each row on/off enable 0 : disable 1 : enable
LV5230BG no.a1741-21/28 address : 08h colsw1 08h colsw1 d7 d6 d5 d4 d3 d2 d1 d0 register name colswen - - - - - - colsw17 r/w w w default 0 0 d0 : colsw17 row 17 display on/off 0 : on 1 : off d7 : colswen column on/off enable 0 : disable 1 : enable address : 09h colsw2 09h colsw2 d7 d6 d5 d4 d3 d2 d1 d0 register name colsw16 colsw15 colsw14 colsw13 colsw12 colsw11 colsw10 colsw9 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 d0 : colsw9 column 9 display on/off 0 : on 1 : off d1 : colsw10 column 10 display on/off 0 : on 1 : off d2 : colsw11 column 11 display on/off 0 : on 1 : off d3 : colsw12 column 12 display on/off 0 : on 1 : off d4 : colsw13 column 13 display on/off 0 : on 1 : off d5 : colsw14 column 14 display on/off 0 : on 1 : off d6 : colsw15 column 15 display on/off 0 : on 1 : off d7 : colsw16 column 16 display on/off 0 : on 1 : off
LV5230BG no.a1741-22/28 address : 0ah colsw3 0ah colsw3 d7 d6 d5 d4 d3 d2 d1 d0 register name colsw8 colsw7 colsw6 colsw5 colsw4 colsw3 colsw2 colsw1 r/w w w w w w w w w default 0 0 0 0 0 0 0 0 d0 : colsw1 column 1 display on/off 0 : on 1 : off d1 : colsw2 column 2 display on/off 0 : on 1 : off d2 : colsw3 column 3 display on/off 0 : on 1 : off d3 : colsw4 column 4 display on/off 0 : on 1 : off d4 : colsw5 column 5 display on/off 0 : on 1 : off d5 : colsw6 column 6 display on/off 0 : on 1 : off d6 : colsw7 column 7 display on/off 0 : on 1 : off d7 : colsw8 column 8 display on/off 0 : on 1 : off
LV5230BG no.a1741-23/28 address : 0bh dfcon1 0bh dfcon1 d7 d6 d5 d4 d3 d2 d1 d0 register name dfen dfgo - - dfdir dfnum [2] dfnum [1] dfnum [0] r/w w w w w w w default 0 0 0 0 0 0 d2 to d0 : dfnum number of palette to be faded to 0 : invalid 1 to 7 : correspond to pwmduty1 to pwmduty7. d3 : dfdir fading direction 0 : fade in 1 : fade out d6 : dfgo fade start 0 : standby 1 : start d7 : dfen fade enable 0 : disable 1 : enable * the interrupt flag is set high after a fade ope ration has completed. manual clearing is required. address : 0ch dfcon2 0ch dfcon2 d7 d6 d5 d4 d3 d2 d1 d0 register name - - - - dfsp [3] dfsp [2] dfsp [1] dfsp [0] r/w w w w w default 0 0 0 0 d3 to d0 : dfsp fading speed per grayscale d3 d2 d1 d0 0 0 0 0 2ms 0 0 0 1 4ms 0 0 1 0 6ms 0 0 1 1 8ms 0 1 0 0 10ms 0 1 0 1 12ms 0 1 1 0 14ms 0 1 1 1 16ms 1 0 0 0 18ms 1 0 0 1 20ms 1 0 1 0 22ms 1 0 1 1 24ms 1 1 0 0 26ms 1 1 0 1 28ms 1 1 1 0 30ms 1 1 1 1 32ms
LV5230BG no.a1741-24/28 address : 0dh maxduty 0dh maxduty d7 d6 d5 d4 d3 d2 d1 d0 register name - - mxdty [5] mxdty [4] mxdty [3] mxdty [2] mxdty [1] mxdty [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : mxdty maximum duty value n : 0 to 63 maximum duty value (n/64) 100[%] * 100[%] when n = 63. address : 10h pwmduty1 10h pwmduty1 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty1 [5] duty1 [4] duty1 [3] duty1 [2] duty1 [1] duty1 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty1 duty value for brightness 1 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0. address : 11h pwmduty2 11h pwmduty2 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty2 [5] duty2 [4] duty2 [3] duty2 [2] duty2 [1] duty2 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty2 duty value for brightness 2 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0. address : 12h pwmduty3 12h pwmduty3 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty3 [5] duty3 [4] duty3 [3] duty3 [2] duty3 [1] duty3 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty3 duty value for brightness 3 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0. address : 13h pwmduty4 13h pwmduty4 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty4 [5] duty4 [4] duty4 [3] duty4 [2] duty4 [1] duty4 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty4 duty value for brightness 4 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0.
LV5230BG no.a1741-25/28 address : 14h pwmduty5 14h pwmduty5 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty5 [5] duty5 [4] duty5 [3] duty5 [2] duty5 [1] duty5 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty5 duty factor value for brightness 5 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0. address : 15h pwmduty6 15h pwmduty6 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty6 [5] duty6 [4] duty6 [3] duty6 [2] duty6 [1] duty6 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty6 duty factor value for brightness 6 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0. address : 16h pwmduty7 16h pwmduty7 d7 d6 d5 d4 d3 d2 d1 d0 register name - - duty7 [5] duty7 [4] duty7 [3] duty7 [2] duty7 [1] duty7 [0] r/w w w w w w w default 0 0 0 0 0 0 d5 to d0 : duty7 duty factor value for brightness 7 setting n : 0 to 63 duty value ((n + 1)/64) 100 [%] * 0 [%] when n = 0.
LV5230BG no.a1741-26/28 address : 20h to 9dh framedata 20h to 9dh framedata d7 d6 d5 d4 d3 d2 d1 d0 register name brn lmn [2] lmn [1] lmn [0] brm lmm [2] lmm [1] lmm [0] r/w w w w w w w w w default 0 0 0 0 0 0 0 0 d2 to d0 : lm11m frame 1 : vertical 1st : horizontal (n + 1) th led brightness d2 d1 d0 0 0 0 off 0 0 1 on at brightness set by pwmduty1 register 0 1 0 on at brightness set by pwmduty2 register 0 1 1 on at brightness set by pwmduty3 register 1 0 0 on at brightness set by pwmduty4 register 1 0 1 on at brightness set by pwmduty5 register 1 1 0 on at brightness set by pwmduty6 register 1 1 1 on at brightness set by pwmduty7 register d3 : br11m frame 1 : vertical 1: horizontal (n + 1) th led flashing/brightness inversion enable 0 : flashing/brightness inversion disabled 1 : flashing/brightness inversion enabled d6 to d4 : lm11n frame 1 : vertical 1 : horizontal (n) th led brightness d2 d1 d0 0 0 0 off 0 0 1 on at brightness set by pwmduty1 register 0 1 0 on at brightness set by pwmduty2 register 0 1 1 on at brightness set by pwmduty3 register 1 0 0 on at brightness set by pwmduty4 register 1 0 1 on at brightness set by pwmduty5 register 1 1 0 on at brightness set by pwmduty6 register 1 1 1 on at brightness set by pwmduty7 register d7 : br11n frame 1 : vertical 1 : horizontal (n) th led flashing/brightness inversion enable 0 : flashing/brightness inversion disabled 1 : flashing/brightness inversion enabled * these are used for each led data. one register is loaded with two leds data. see the table on the following pa ge for the storage address of each dot.
LV5230BG no.a1741-27/28 frame data register tables xxh : higher-order 4 bits of register xx xxl : lower-order 4 bits of register xx 17 7 mode frame 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 20h 20l 21h 21l 22h 22l 23h 23l 24h 24l 25h 25l 26h 26l 27h 27l 28h 2 29h 29l 2ah 2al 2bh 2bl 2ch 2cl 2dh 2dl 2eh 2el 2fh 2fl 30h 30l 31h 3 32h 32l 33h 33l 34h 34l 35h 35l 36h 36l 37h 37l 38h 38l 39h 39l 3ah 4 3bh 3bl 3ch 3cl 3dh 3dl 3eh 3el 3fh 3fl 40h 40l 41h 41l 42h 42l 43h 5 44h 44l 45h 45l 46h 46l 47h 47l 48h 48l 49h 49l 4ah 4al 4bh 4bl 4ch 6 4dh 4dl 4eh 4el 4fh 4fl 50h 50l 51h 51l 52h 52l 53h 53l 54h 54l 55h 7 56h 56l 57h 57l 58h 58l 59h 59l 5ah 5al 5bh 5bl 5ch 5cl 5dh 5dl 5eh frame 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 5fh 5fl 60h 60l 61h 61l 62h 62l 63h 63l 64h 64l 65h 65l 66h 66l 67h 2 68h 68l 69h 69l 6ah 6al 6bh 6bl 6ch 6cl 6dh 6dl 6eh 6el 6fh 6fl 70h 3 71h 71l 72h 72l 73h 73l 74h 74l 75h 75l 76h 76l 77h 77l 78h 78l 79h 4 7ah 7al 7bh 7bl 7ch 7cl 7dh 7dl 7eh 7el 7fh 7fl 80h 80l 81h 81l 82h 5 83h 83l 84h 84l 85h 85l 86h 86l 87h 87l 88h 88l 89h 89l 8ah 8al 8bh 6 8ch 8cl 8dh 8dl 8eh 8el 8fh 8fl 90h 90l 91h 91l 92h 92l 93h 93l 94h 7 95h 95l 96h 96l 97h 97l 98h 98l 99h 99l 9ah 9al 9bh 9bl 9ch 9cl 9dh 15 5 mode frame 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 20h 20l 21h 21l 22h 22l 23h 23l 24h 24l 25h 25l 26h 26l 27h 2 29h 29l 2ah 2al 2bh 2bl 2ch 2cl 2dh 2dl 2eh 2el 2fh 2fl 30h 3 32h 32l 33h 33l 34h 34l 35h 35l 36h 36l 37h 37l 38h 38l 39h 4 3bh 3bl 3ch 3cl 3dh 3dl 3eh 3el 3fh 3fl 40h 40l 41h 41l 42h 5 44h 44l 45h 45l 46h 46l 47h 47l 48h 48l 49h 49l 4ah 4al 4bh frame 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 4dh 4dl 4eh 4el 4fh 4fl 50h 50l 51h 51l 52h 52l 53h 53l 54h 2 56h 56l 57h 57l 58h 58l 59h 59l 5ah 5al 5bh 5bl 5ch 5cl 5dh 3 5fh 5fl 60h 60l 61h 61l 62h 62l 63h 63l 64h 64l 65h 65l 66h 4 68h 68l 69h 69l 6ah 6al 6bh 6bl 6ch 6cl 6dh 6dl 6eh 6el 6fh 5 71h 71l 72h 72l 73h 73l 74h 74l 75h 75l 76h 76l 77h 77l 78h
LV5230BG ps no.a1741-28/28 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. address : ffh status ffh status d7 d6 d5 d4 d3 d2 d1 d0 register name - - - - - dfif fedif scrif r/w r r r default x x x x x d0 : scrif end of scroll interrupt occurrence flag 0 : no end of scroll interrupt has occurred. 1 : an end of scroll interrupt has occurred. * the flag needs to be cleared manually (ctrl1.scrlclr). d1 : fedif end of fade interrupt occurrence flag 0 : no end of fade interrupt has occurred. 1 : an end of fade interrupt has occurred. * the flag needs to be cleared manually (ctrl1.fadeclr). d2 : dfif end of palette fade interrupt occurrence flag 0 : no end of palette fade interrupt has occurred. 1 : an end of palette fade interrupt has occurred. * the flag needs to be cleared manually (ctrl1.dfclr). the or of scrif, fedif and dfif appear at the interrupt pin. * the addresses used here are all dummy and not used in actual communications. this catalog provides information as of october, 2010. specifications and information herein are subject to change without notice.

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